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Data Sheet
ADuM4160
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
4.5 V ≤ V BUS1 ≤ 5.5 V, 4.5 V ≤ V BUS2 ≤ 5.5 V; 3.1 V ≤ V DD1 ≤ 3.6 V, 3.1 V ≤ V DD2 ≤ 3.6 V; all minimum/maximum specifications apply over
the entire recommended operation range, unless otherwise noted; all typical specifications are at T A = 25°C, V DD1 = V DD2 = 3.3 V. Each
voltage is relative to its respective ground.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Total Supply Current 1
1.5 Mbps
V DD1 or V BUS1 Supply Current
V DD2 or V BUS2 Supply Current
I DD1 (L)
I DD2 (L)
5
5
7
7
mA
mA
750 kHz logic signal rate C L = 450 pF
750 kHz logic signal rate C L = 450 pF
12 Mbps
V DD1 or V BUS1 Supply Current
V DD2 or V BUS2 Supply Current
I DD1 (F)
I DD2 (F)
6
6
8
8
mA
mA
6 MHz logic signal rate C L = 50 pF
6 MHz logic signal rate C L = 50 pF
Idle Current
V DD1 or V BUS1 Idle Current
I DD1 (I)
1.7
2.3
mA
Input Currents
I DD? , I DD+ ,
?1
+0.1
+1
μA
0 V ≤ V DD? , V DD+ , V UD+ , V UD? , V SPD , V PIN ,
I UD+ , I UD? ,
I SPD , I PIN ,
I SPU , I PDEN
V SPU , V PDEN ≤ 3.0
Single-Ended Logic High Input Threshold
Single-Ended Logic Low Input Threshold
Single-Ended Input Hysteresis
V IH
V IL
V HST
2.0
0.4
0.8
V
V
V
Differential Input Sensitivity
V DI
0.2
V
|V XD+ ? V XD? |
Logic High Output Voltages
Logic Low Output Voltages
V DD1 and V DD2 Supply Undervoltage Lockout
V BUS1 Supply Undervoltage Lockout
V BUS2 Supply Undervoltage Lockout
Transceiver Capacitance
V OH
V OL
V UVLO
V UVLOB1
V UVLOB2
C IN
2.8
0
2.4
3.5
3.5
10
3.6
0.3
3.1
4.35
4.4
V
V
V
V
V
pF
R L = 15 kΩ, V L = 0 V
R L = 1.5 kΩ, V L = 3.6 V
UD+, UD?, DD+, DD? to ground
Capacitance Matching
10
%
Full Speed Driver Impedance
Impedance Matching
Z OUTH
4
10
20
Ω
%
SWITCHING SPECIFICATIONS, I/O PINS LOW SPEED
Low Speed Data Rate
1.5
Mbps C L = 50 pF
Propagation Delay 2
t PHLL , t PLHL
325
ns
C L = 50 pF, SPD = SPU = low,
V DD1 , V DD2 = 3.3 V
Side 1 Output Rise/Fall Time (10% to 90%) Low
t RL /t FL
75
300
ns
C L = 450 pF, SPD = SPU = low,
Speed
V DD1 , V DD2 = 3.3 V
Low Speed Differential Jitter, Next Transition
Low Speed Differential Jitter, Paired Transition
|t LJN |
|t LJP |
45
15
ns C L = 50 pF
ns C L = 50 pF
SWITCHING SPECIFICATIONS, I/O PINS FULL SPEED
Full Speed Data Rate
12
Mbps C L = 50 pF
Propagation Delay 2
t PHLF , t PLHF
20
60
70
ns
C L = 50 pF, SPD = SPU = high,
V DD1 , V DD2 = 3.3 V
Output Rise/Fall Time (10% to 90%) Full Speed
t RF /t FF
4
20
ns
C L = 50 pF, SPD = SPU = high,
V DD1 , V DD2 = 3.3 V
Full Speed Differential Jitter, Next Transition
Full Speed Differential Jitter, Paired Transition
|t FJN |
|t FJP |
3
1
ns C L = 50 pF
ns C L = 50 pF
Rev. D | Page 3 of 16
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